This invention relates to random access memories (RAM), and in particular to systems and methods for controlling a RAM having multiple data banks.
Data processing systems such as personal computers, digital video players, and wireless communications devices often include multiple data processing clients which share access to random access memory (RAM). Conventional RAM includes static RAM (SRAM) and dynamic RAM (DRAM). Commonly-used DRAM includes synchronous DRAM (SDRAM) such as double-data-rate SDRAM (DDR-SDRAM). Technological improvements have led to great increases in computing speed and RAM capacity. Furthermore, typical systems include increasing numbers of clients sharing access to RAM. In this context, efficient usage of available RAM bandwidth is becoming increasingly important.
Some RAM units, such as typical SDRAM units, can include a plurality of memory banks. Each memory bank comprises an array of memory locations organized in pages (rows). Each memory location within the RAM is characterized by a row (page) address, and a column address. Reading or writing data at a given location within the RAM typically requires a number of pre-read/write memory operations such as activate and precharge. Activate commands open pages within a bank, while precharge commands close the bank. Such operations can involve a latency overhead of a few to tens of clock cycles per read/write transactions. Typically, only one page at a time can be open within any given bank. Consequently, if one or more clients require consecutive access to different pages within the same bank, a significant number of clock cycles can be wasted as the first page is closed and the second page is opened. The latency overhead associated with pre-read/write commands can substantially constrain the utilization of available RAM bandwidth.